A substantial amount of research in electronic microsystems has focused on bringing more computing power to smaller devices. Traditional approaches to increase computing bandwidth has often focused on exploiting concurrency, such as by allocating increasingly more gates to specific tasks, or by performing instructions faster, such as operating gates at higher speeds. These traditional approaches are expected to have diminishing returns, and may bump up against technological barriers, such as for example limitations on power dissipation.
Another technological barrier has to do with the substantial increase in the number of transistors built in modern devices, which increases by approximately a factor of two every 18 to 24 months, and which is predicted by Moore's Law. As the number of devices increases, more and more area on a chip needs to be devoted to interconnects. At some point, the portion of the chip devoted to interconnects becomes excessive, possibly exceeding the area of the chip devoted to transistors or active devices.
Also known in the prior art is Adler et al., U.S. Pat. No. 4,463,344, issued Jul. 31, 1984, which is said to disclose an algorithm and the hardware embodiment for producing a run length limited code useful in magnetic recording channels. The system described produces sequences which have a minimum of 2 zeros and a maximum of 7 zeros between adjacent 1's. The code is generated by a sequential scheme that maps 1 bit of unconstrained into 2 bits of constrained data. The encoder is a finite state machine whose internal state description requires 3 bits. It possesses the attractive feature of reset data blocks which reset it to a fixed state. The decoder requires a look ahead of three future channel symbols (6 bits) and its operation is channel state independent. The error propagation due to a random error is 3 bits. The hardware implementation is extremely simple and can operate at very high data speeds.
Also known in the prior art is Deogun et al., U.S. Pat. No. 7,088,141, issued Aug. 8, 2006, which is said to disclose a multi-threshold complementary metal-oxide semiconductor (MTCMO) bus circuit reduces bus power consumption via a reduced circuit leakage standby and pulsed control of standby mode so that the advantages of MTCMOS repeater design are realized in dynamic operation. A pulse generator pulses the high-threshold voltage power supply rail standby switching devices in response to changes detected at the bus circuit inputs. The delay penalty associated with leaving the standby mode is overcome by reducing cross-talk induced delay via a cross-talk noise minimization encoding and decoding scheme. A subgroup of bus wires is encoded and decoded, simplifying the encoding, decoding and change detection logic and results in the bus subgroup being taken out of standby mode only when changes occur in one or more of the subgroup inputs, further reducing the power consumption of the overall bus circuit.
Also known in the prior art is Rijavec, U.S. Patent Application Publication No. 2007/0176800 A1, published Aug. 2, 2007, which is said to disclose methods and systems for improving performance of data decoding using a priori information about the data steam. In one aspect a decoder may determine the degree of lossiness inherent in the data or in the application of the data as a maximum resolution of data to be decoded and may thereby streamline entropy decoding of the data. For example, in DCT-based image data compression coupled with Huffman or other entropy encoding, a priori data may be analyzed to determine the maximum required resolution in bits of the DCT encoded data so as to simplify the entropy decoding. Other aspects optimize DCT decoding computation with faster approximations where the quantization values indicate a higher degree of lossiness or noise in the DCT encoded data. A priori information may generally comprise values in the quantization table of a DCT encoded image and may be analyzed to determine the maximum symbol size and/or degree of lossiness.
Also known in the prior art is Noda, U.S. Pat. No. 7,339,500, issued Mar. 4, 2008, which is said to disclose two different block codes that can be encoded by one-type of encoding section. A first-point-fixed encoding section divides m-bit data into a first-half code and a second-half code, and encodes them into an n-bit provisional code with fixed start-point state. A code A/B counter receives a reset-signal and outputs a code selection signal to a code-order reversing section and a top-code correction section. The code-order reversing section receives a codeword excluding the top code from the start-point-fixed encoding section; and outputs the codeword as is, when the code selection signal indicates a code B, and reverses the order of the codeword to generate a new codeword, and outputs the new codeword to a latch, when the code selection signal indicates a code A. The top-code correction section determines whether the top code needs to be modified, and modifies the top code, if necessary.
Also known in the prior art is Motoyama, U.S. Patent Application Publication No. 2008/0094260 A1, published Apr. 24, 2008, which is said to disclose a logic circuit that executes a prescribed arithmetic processing that includes a decoder that converts one or more binary input data into a first plurality of bit data of a constant hamming weight regardless of a hamming weight of the input data, an interconnect network that is connected to the decoder, changes a bit pattern of the first plurality of bit data and generates a second plurality of bit data, according to receiving the first plurality of bit data converted according to the decoder, and substituting a bit position of the received first plurality of bit data for the purpose of the prescribed arithmetic operation, and an encoder connected to the interconnect network and converts the second plurality of bit data generated in the interconnect network into one or more binary output data.
Also known in the prior art is Motoyama, U.S. Patent Application Publication No. 2008/0212776 A1, published Sep. 4, 2008, which is said to disclose an encryption processing circuit that includes a decoder configured to convert a binary input data used for predetermined encryption computing into a first plurality of bit data of a constant hamming weight independently of a hamming weight of the input data; a wiring network configured to receive the first plurality of bit data converted by the decoder, the wiring network further configured, for the purpose of the predetermined encryption computing, to change a bit pattern of the received first plurality of bit data by replacing bit positions of the first plurality of bit data, and to generate a second plurality of bit data; and an encoder configured to convert the second plurality of bit data generated in the wiring network into a binary output data.
Mechanical computation systems that rely on a plurality of states, including machines that operate using N=10 states, such as Babbage's Difference Engine, have been known for many years. However, electronic computation systems use two states (e.g., binary logic).
There is a need for electronic logic gates and electronic computational systems that use more logic states than two binary logic states.